Fasciculus:CMOS OR.svg

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Sua resolutio ‎(fasciculus SVG, nominale 375 × 250 elementa imaginalia, magnitudo fasciculi: 4 chiliocteti)

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Summarium

Descriptio Layout of NMOS and PMOS components in an OR Gate. This OR gate is implemented as an AND gate with both inputs inverted(by using PMOS at the top) as well as the output (inverter at the right) which is functionally correct, but is not commonly used as it requires 2 extra transistors.
Datum
Fons Own work using: Inkscape 0.43
Auctor inductiveload
SVG genesis
InfoField
 
The SVG code is valid.
 
This circuit diagram was created with Inkscape.

Potestas usoris

Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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depicts Anglica

inceptio

12 Iulii 2006

MIME type Anglica

image/svg+xml

checksum Anglica

2ac5c0cd9f4d75d5b703c0e944ed1991659938c2

modus determinationis: SHA-1 Anglica

data size Anglica

4 161 byte

altitudo

250 pixel

latitudo

375 pixel

Historia fasciculi

Presso die vel tempore fasciculum videbis, sicut tunc temporis apparuit.

Dies/TempusMinutioDimensionesUsorSententia
recentissima18:24, 21 Ianuarii 2020Minutum speculum redactionis 18:24, 21 Ianuarii 2020 factae375 × 250 (4 chiliocteti)GKFXUse <text> rather than text as path to give better thumbnails
19:25, 24 Martii 2014Minutum speculum redactionis 19:25, 24 Martii 2014 factae375 × 250 (21 chiliocteti)Wereldburger758Valid SVG now.
19:40, 12 Iulii 2006Minutum speculum redactionis 19:40, 12 Iulii 2006 factae375 × 250 (29 chiliocteti)Inductiveload{{Information |Description=Layout of NMOS and PMOS components in an OR Gate |Source=Own drawing, Inkscape 0.43 |Date=12/07/06 |Author=inductiveload |Permission=PD |other_versions= }} Category:CMOS

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